Non-Computational Instructions in the 8086 from 8087 to P6

Martin F. Johansen, 2023-04-23

In the previous article, we covered the non-computational instructions of the classic 8086. Let's now look at the non-computational instructions in the extensions that followed.

See if you know all the non-computational instructions, and see below for comments on them.

8087's Non-Computational Instructions

The 8087 floating point coprocessor has about 71 instructions, and non of them are non-computational. This might not be a surprise as the point of the coprocessor was to do computations and not control other parts of the computer.

80186's Non-Computational Instructions

There are 9 additional instructions added to the 80186, among them 5 are non-computational.


These are mainly a matter of speed and convenience. The BOUND instruction is a combined check and software interrupt. The following two pairs are string variants of the IN and OUT instructions.

80286's Non-Computational Instructions

With the 80286, x86-series of processors were now going to be used for multi-user operating systems. The instructions provide access to virtual memory and virtual processors. Among the 17 new instructions, 5 are non-computational.


The CLTS instruction clears the TS flag. When set, it causes coprocessor instructions to fail.

The LGDT and LDTR instructions control the memory manager device. They affect how all other instructions that deal with memory work, and whether they work at all for a given program.

The LIDT instruction controls where the functions are that are triggered by interrupts. This can drastically change how the computer operates.

The LTR instruction deals with multitasking, when one CPU is used for running more than one program.

The LMSW instruction loads various settings of the CPU, for example, whether virtual memory is used and whether it has a coprocessor. Clearly a non-computational instruction.

80386's Non-Computational Instructions

The 80386 mostly extended the instruction set with a few variants of existing features. There are about 70 new instructions, depending on how you count, and only 8 of them are non-computational.


INSD and OUTSD are new variants of the original IN and OUT instructions.

The POPFD and IRETD/IRETF are also variants of the original POPF and IRET.

The MOV instruction gets infrastructural variants to configure the Control Registers (CR), Debug Registers (DR) and Test Registers (TR). The control register is used for various configurations of the CPU. The debug register is used to create debuggers by managing where to stop program or step through them. The test registers were used to test some aspects of the memory controller.

80486's Non-Computational Instructions

Among the 8 added instructions, 3 are non-computational.


The INVLPG instruction deals with issues related to reconfiguring the memory management device and virtual memory.

The INVD and WBINVD instructions controls caches on the CPU. The caches can be seen as a separate device between the CPU and the memory. The INVD instruction instructs the cache to drop all its data, and not commit it to memory. The WBINVD instruction does write the cached data to memory. This can influence the speed of the upcoming instructions, as recently used memory is no longer caches.

P5/P6's Non-Computational Instructions


The WRMSR instruction writes various settings that control how the CPU works.

The RSM instruction is related to an even more privileged mode than the OS works in.

The RDTSC instruction reads the number of cycles that have ocurred since the CPU started. This can be seen as a high precision clock. It is clearly a non-computational instruction, as it only reads a register controlled by separate mechanisms.

The UD2 instruction will cause an exception when run. As such, it is a variant of the INT instruction.

The SYSCALL and SYSRET instructions are new variants of INT and IRET instructions.

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